Title Die images ScrapCPU TinyTapeout (2 imgs) TinyTapeout table Logisim screenshot Notes scan Test case img, actions flow img TBB1143 logisim screenshot Minecraft redstone clock Ring oscillator actions flow screenshot, bad test case screenshot logisim ring osc screenshot bad verilog screenshot DO NOT MAKE A RING OSC IN VERILOG synthesis impossible, timing issues LCD screen Check your sim models especially if third party never blindly rely compare to datasheets OpenShuttle GF180 5V TWO WEEKS 2650 pic chip pics the bug list is 9 items can't add entire addressing mode broke 25MHz limit barely standing caravel overview gpio pin overview power-up IO config wrong GPIO_MODE_MGMT_* GPIO_MODE_USER_* AS2650 has no pins Same reset pin cannot reset only once must reset after IO config infinite loop interdigit carry Useless BCD Don't care Indirect, relative addressed branches broken don't branch indirect, absolute works Index addressing only on load/store loda example adda example 2 works, 6 doesn't return instr takes 256 clocks FSM bug 8-bit counter forgot to reset CPU has to wait for counter FSM screenshot push writes to wrong location messed up stack pointer decrement push address off by one indirect indexed storers don't work example does nothing makex indexed addressing even more broken the CPU can't add or sub Add computes ... bad example good example CPU incorrectly asserts that ... substracts also wrong: ... code becomes bloated due to workaround + 2 screenshots conclusion: its BAD! How did this happen? I did verification ... ... ... ... Right? On sky130, testing framework can do RTL and GL gf180 didn't have this had to throw together my own thing Start sim with CPU and RAM Let CPU run program Check if results match expectation END Wait, that's it? No individual test case for each instr no checking cycles no checking bus cycles simulated using ideal RAM no edge cases considered low opcode coverage FSM should halt on undefined states factor out memory addressing in general, keep FSM simple and DOCUMENT IT Name your signals bad code screenshot having an instruction take a clock longer OR have it not work at all code style IS important time management learn how to budget time learn about your tools dbus_in screenshot external bus limits CPU expects instant memory response OPACK no OPACK really fast screm is slow Chip IO buffers slow signals 25MHz instead of theoretical 50MHz did not make enough use of caravel did not use WB did not use LA came very close almost ran real-world software - recommend this badge pic same gf180 node (gfmpw-1) last chance AS2650-2 and 11 other things deadline is in 5 weeks 100% of my power as2650-2 not just fixed, but upgraded Same CPU core, but extended ISA more sane external bus and INTERRUPTS built-in peripherals internal RAM bootstrap ROM making use of WB layout screenshot directory screenshot still had a lot of time left a second submission: multi project multiplexer name gfmpw1-multi LED Blinker Dual-SID SN76489 AY8913 TBB1143 MC14500 QCPU Diceroll Hellorld! UE14500 AS-11 Risc-V layout screenshots photos x2 photo directory screenshot MC14500 - perfect R-V - one minor bug due to simulation skip SID - perfect SN76468 & AY8913 - TBD Hellorld, Blinker, TBB1143, Diceroll - Perfect QCPU RISC MCU GPIO ports, timers, pwm, interrupts 64 bytes RAM (shared) 32KWord ROM external winbond flash pic ROM is a winbond flash Default: SPI Optional: QSPI 32 cycles per fetch vs 8 cycles execution takes one clock release from d. power down continuous read mode exist write enable write status register quad read many quad reads screenshot of file header screenshot of gtkwave QCPU voltage level differences level shifter forgor to simulate it broken fixable with clever use of 74-series logic (annoying) still doesn't work status registers are stored in flash flash needs time sending more commands crashes IC remember verilog model? a 30 second look at datasheet revealed problem READ YOUR DATASHEETS! CHECK MODEL CODE YOURSELF! mgmt comes in clutch can override CS s ignal inhibit WR status reg regs are non volatile inline asm code screenshot AS-11 PDP-11/40 compatible promising in sim still discovered issues div instr is wrong PC-relative addressing is wrong as in, different function as verified! div does not produce modulo PC-relative differences RTFM look at example code / binaries AS-11 cannot access FRAM AS-11 multiplexes address/data gtkwave screenshot osc trace screenshot clock anding code screenshot logisim screenshot osc trace screenshot osc trace screenshot with red circle LPF diagramm never, ever AND the clock actually a novel problem did not show in GL sim ...in iverilog Verilator DID simulate this correctly could affect combinatorial logic listen to advice you're given? Final line of defense is your own intellect and intuition? Shit happens? AS2650-2 Has 0 discovered bugs Runs at 54MHz Earned a permanent spot on my breadboard other people interested photo of breadboard paid shuttle run - CI2406 skywater 130nm 1.8V Z80, 6502, 1802, 8x305 ScrapCPU VLIW Re-used broken flash iface it takes months ... layout screenshots VLIW has broken icache some minor GPIO issues efabless sent wrong git commit, then went bankrupt final lesson: It is possible to commit no mistakes and still loose! That is life Aka someone ELSE fucked up! Not me! started doing manual layout, i.e. SCLs analog circuitry with new frontiers comes new mistakes Infact, taped out DRC errors with SCL! analog stuff screenshot BONUS TIP! Documentation! not just for others, also for yourself trust me, you will NEED IT! you save more time in frustrated debugging than you put into writing it. Also really REALLY impressed people in my case! docs screenshot docs screenshot That's it for the presentation I am not done making mistakes could talk for hours about designs maybe I will? I am working on more stuff! next tapeout: retro and homebrew stuff Avalon Semiconductors? be super cute EOF